The following training materials are available for Riviera-PRO 2007.10.
| Course |
Training Module |
File |
| 0 |
Overview |
 |
| 1 |
GUI/Batch mode - Basics of operation in GUI and batch mode; scripter modes |
|
| 2 |
Design Entry - Using the HDL Editor |
|
| 3 |
Libraries - Creating, mapping, refreshing, encrypting simulation libraries |
|
| 4 |
HDL Compilation - Compiling HDL files and EDIF netlist |
|
| 5 |
Simulation - Simulation initialization |
|
| 6 |
Debugging - HDL code tracing, simulation breakpoints, watch window, list viewer, waveform viewer, memory viewer, processes window, process stack window, advance dataflow viewer |
|
| 7 |
Code, Toggle and Expression Coverage - Getting code coverage, toggle coverage and expression coverage (Verilog only) statistics for the design; merging coverage reports |
|
| 8 |
Design Profiler - Profiling the simulation time of the design |
|
| 8a |
Design Profiler Verilog - Profiling the simulation time of the Verilog design |
|
| 8b |
Design Profiler VHDL - Profiling the simulation time of the VHDL design |
|
| 9 |
PLI Applications - Compiling and running the PLI application |
|
| 10 |
Assertion Based Verification - Using OVA, PSL and SysemVerilog (assertion subset) languages |
|
| 11 |
SLP Simulation - Using accelerated simulation engine for Verilog designs |
|
| 12 |
Comparing Waveforms - How to compare ASDB and VCD waveform files |
|
| 13 |
SystemC Simulation - Native SystemC simulation |
|
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